The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a recess gate and a method of fabricating the same.
Recently, with the high integration of semiconductor memory devices, the devices shrink in size and patterns become fine. As the size of the device becomes smaller, a gate channel length is also reduced so that an operational speed or input/output rate of information becomes slower due to a leakage current caused by short channel effect, hot carrier effect and so on.
To prevent this phenomenon, there has been proposed various structured recess gates for securing a channel length. Among them, a bulb recess gate, which has been put to practical use in recent years, and is being actively researched because it has an advantage of securing the channel length effectively. The bulb recess gate is configured with an upper portion with a vertical shape and a lower portion with a bulb shape.
FIG. 1 illustrates a cross-sectional view showing a typical method of fabricating a recess gate in a semiconductor device. A device isolation structure 12 is formed in a predetermined region of a semiconductor substrate 11 to define an active region and a field region. The semiconductor substrate 11 of the active region is selectively etched to form a bulb recess 13. The bulb recess 13 has an upper vertical portion 13A and a lower bulb shaped portion 13B. A gate insulating layer 14 is formed on the semiconductor substrate 11 where the bulb recess 13 is formed. A gate conductive layer is formed on the gate insulating layer 14 such that it is filled into the bulb recess 13 and protrudes higher than the top surface of the semiconductor substrate 11. Herein, the gate conductive layer comprises a polysilicon layer 15 and a metal or metal silicide layer 16, which are stacked in sequence.
As described above, the bulb recess gate is used for widening the channel length. However, since the upper vertical portion 13A of the bulb recess 13 is narrow but the lower bulb shaped portion 13B is rounded, the polysilicon layer 15 is not completely filled into the bulb shaped portion 13B so that a seam A occurs in the polysilicon layer 15.
In addition, the lower bulb shaped portion 13B of the bulb recess 13 is formed using an isotropic etch process, which leads to another limitation that there are sharp portions B where the upper vertical portion 13A and the bulb shaped portion 13B meet together. This sharp portion B has an adverse effect on device characteristics, e.g., deterioration of the gate insulating layer 14.
FIG. 2 illustrates a transmission electron microscope (TEM) micrograph showing the limitations according to the typical method. A polysilicon layer may not be completely filled into a recess and thus a seam occurs in the polysilicon layer.